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Liers, Frauke, Nieberg, Tim and Pardella, Gregor (2011). Via Minimization in VLSI Chip Design - Application of a Planar Max-Cut Algorithm. Working Paper.
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Liers, Frauke, Nieberg, Tim and Pardella, Gregor (2011). Via Minimization in VLSI Chip Design - Application of a Planar Max-Cut Algorithm. Working Paper.